EE215A Analog Integrated Circuit Design

Table of contents

1. EE215A Analog Integrated Circuit Design
   1. 1. Introduction to Analog Design
   2. 2. Basic MOS Device Physics
   3. 3. Single-Stage Amplifiers
   4. 4. Differential Amplifiers
   5. 5. Current Mirrors and Biasing Techniques
   6. 6. Frequency Response of Amplifiers
   7. 7. Noise
   8. 8. Feedback
   9. 9. Operational Amplifiers
   10. 10. Stability and Frequency Compensation
   11. 11. Nanometer Design Studies
   12. 12. Bandgap References
   13. 13. Introduction to Switched-Capacitor Circuits
   14. 14. Nonlinearity and Mismatch
   15. 15. Oscillators
   16. 16. Phase-Locked Loops
   17. 17. Short-Channel Effects and Device Models
   18. 18. CMOS Processing Technology
   19. 19. Layout and Packaging

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EE215A Analog Integrated Circuit Design

1. Introduction to Analog Design

• Introduction to Analog Design
  • 1.1 Why Analog?
    • 1.1.1 Sensing and Processing Signals
    • 1.1.2 When Digital Signals Become Analog
    • 1.1.3 Analog Design Is in Great Demand
    • 1.1.4 Analog Design Challenges
  • 1.2 Why Integrated?
  • 1.3 Why CMOS?
  • 1.4 Why This Book?
  • 1.5 Levels of Abstraction

2. Basic MOS Device Physics

• 2. Basic MOS Device Physics
  • 2.1 General Considerations
    • 2.1.1 MOSFET as a Switch
    • 2.1.2 MOSFET Structure
    • 2.1.3 MOS Symbols
  • 2.2 MOS I/V Characteristics
    • 2.2.1 Threshold Voltage
    • 2.2.2 Derivation of I/V Characteristics
    • 2.2.3 MOS Transconductance
  • 2.3 Second-Order Effects
  • 2.4 MOS Device Models
    • 2.4.1 MOS Device Layout
    • 2.4.2 MOS Device Capacitances
    • 2.4.3 MOS Small-Signal Model
    • 2.4.4 MOS SPICE models
    • 2.4.5 NMOS Versus PMOS Devices
    • 2.4.6 Long-Channel Versus Short-Channel Device:
  • 2.5 Appendix A: FinFETs
  • 2.6 Appendix B: Behavior of a MOS Device as a Capacitor

3. Single-Stage Amplifiers

• 3. Single-Stage Amplifiers
  • 3.1 Applications
  • 3.2 General Considerations
  • 3.3 Common-Source Stage
    • 3.3.1 Common-Source Stage with Resistive Load
    • 3.3.2 CS Stage with Diode-Connected Load
    • 3.3.3 CS Stage with Current-Source Load
    • 3.3.4 CS Stage with Active Load
    • 3.3.5 CS Stage with Triode Load
    • 3.3.6 CS Stage with Source Degeneration
  • 3.4 Source Follower
  • 3.5 Common-Gate Stage
  • 3.6 Cascode Stage
    • 3.6.1 Folded Cascode
  • 3.7 Choice of Device Models

4. Differential Amplifiers

• 4. Differential Amplifiers
  • 4.1 Single-Ended and Differential Operation
  • 4.2 Basic Differential Pair
    • 4.2.1 Qualitative Analysis
    • 4.2.2 Quantitative Analysis
    • 4.2.3 Degenerated Differential Pair
  • 4.3 Common-Mode Response
  • 4.4 Differential Pair with MOS Loads
  • 4.5 Gilbert Cell

5. Current Mirrors and Biasing Techniques

• 5. Current Mirrors and Biasing Techniques
  • 5.1 Basic Current Mirrors
  • 5.2 Cascode Current Mirrors
  • 5.3 Active Current Mirrors
    • 5.3.1 Large-Signal Analysis
    • 5.3.2 Small-Signal Analysis
    • 5.3.3 Common-Mode Properties
    • 5.3.4 Other Properties of Five-Transistor OTA
  • 5.4 Biasing Techniques
    • 5.4.1 CS Biasing
    • 5.4.2 CG Biasing
    • 5.4.3 Source Follower Biasing
    • 5.4.4 Differential Pair Biasing

6. Frequency Response of Amplifiers

• 6. Frequency Response of Amplifiers

  • 6.1 General Considerations
    • 6.1.1 Miller Effect
    • 6.1.2 Association of Poles with Nodes
  • 6.2 Common-Source Stage

  • 6.3 Source Followers

    • 6.4 Common-Gate Stage

    • 6.5 Cascode Stage

      • 6.6 Differential Pair
        • 6.6.1 Differential Pair with Passive Loads
        • 6.6.2 Differential Pair with Active Load
      • 6.7 Gain-Bandwidth Trade-Offs
        • 6.7.1 One-Pole Circuits
        • 6.7.2 Multi-Pole Circuits

    • 6.8 Appendix A: Extra Element Theorem

    • 6.9 Appendix B: Zero-Value Time Constant Method

    • 6.10 Appendix C: Dual of Miller’s Theorem

7. Noise

• 7. Noise
  • 7.1 Statistical Characteristics of Noise
    • 7.1.1 Noise Spectrum
    • 7.1.2 Amplitude Distribution
    • 7.1.3 Correlated and Uncorrelated Sources
    • 7.1.4 Signal-to-Noise Ratio
    • 7.1.5 Noise Analysis Procedure
  • 7.2 Types of Noise
    • 7.2.1 Thermal Noise
    • 7.2.2 Flicker Noise
  • 7.3 Representation of Noise in Circuits
  • 7.4 Noise in Single-Stage Amplifiers
    • 7.4.1 Common-Source Stage
    • 7.4.2 Common-Gate Stage
    • 7.4.3 Source Followers
    • 7.4.4 Cascode Stage
  • 7.5 Noise in Current Mirrors
  • 7.6 Noise in Differential Pairs
  • 7.7 Noise-Power Trade-Off
  • 7.8 Noise Bandwidth
  • 7.9 Problem of Input Noise Integration
  • 7.10 Appendix A: Problem of Noise Correlation

8. Feedback

• 8. Feedback

  • 8.1 General Considerations
    • 8.1.1 Properties of Feedback Circuits
    • 8.1.2 Types of Amplifiers
    • 8.1.3 Sense and Return Mechanisms
  • 8.2 Feedback Topologies
    • 8.2.1 Voltage-Voltage Feedback
    • 8.2.2 Current-Voltage Feedback
    • 8.2.3 Voltage-Current Feedback
    • 8.2.4 Current-Current Feedback

  • 8.3 Effect of Feedback on Noise

    • 8.4 Feedback Analysis Difficulties

      • 8.5 Effect of Loading
        • 8.5.1 Two-Port Network Models
        • 8.5.2 Loading in Voltage-Voltage Feedback
        • 8.5.3 Loading in Current-Voltage Feedback
        • 8.5.4 Loading in Voltage-Current Feedback
        • 8.5.5 Loading in Current-Current Feedback
        • 8.5.6 Summary of Loading Effects
      • 8.6 Bode’s Analysis of Feedback Circuits
        • 8.6.1 Observations
        • 8.6.2 Interpretation of Coefficients
        • 8.6.3 Bode’s Analysis
        • 8.6.4 Blackman’s Impedance Theorem
    • 8.7 Middlebrook’s Method
      • 8.8 Loop Gain Calculation Issues
        • 8.8.1 Preliminary Concepts
        • 8.8.2 Difficulties with Return Ratio
    • 8.9 Alternative Interpretations of Bode’s Method

9. Operational Amplifiers

• 9. Operational Amplifiers
  • 9.1 General Considerations
    • 9.1.1 Performance Parameters
  • 9.2 One-Stage Op Amps
    • 9.2.1 Basic Topologies
    • 9.2.2 Design Procedure
    • 9.2.3 Linear Scaling
    • 9.2.4 Folded-Cascode Op Amps
    • 9.2.5 Folded-Cascode Properties
    • 9.2.6 Design Procedure
  • 9.3 Two-Stage Op Amps
    • 9.3.1 Design Procedure
  • 9.4 Gain Boosting
    • 9.4.1 Basic Idea
    • 9.4.2 Circuit Implementation
    • 9.4.3 Frequency Response
  • 9.5 Comparison
  • 9.6 Output Swing Calculations
  • 9.7 Common-Mode Feedback
    • 9.7.1 Basic Concepts
    • 9.7.2 CM Sensing Techniques
    • 9.7.3 CM Feedback Techniques
    • 9.7.4 CMFB in Two-Stage Op Amps
  • 9.8 Input Range Limitations

  • 9.9 Slew Rate

    • 9.10 High-Slew-Rate Op Amps
      • 9.10.1 One-Stage Op Amps
      • 9.10.2 Two-Stage Op Amps

    • 9.11 Power Supply Rejection

    • 9.12 Noise in Op Amps

10. Stability and Frequency Compensation

• 10. Stability and Frequency Compensation
  • 10.1 General Considerations
  • 10.2 Multipole Systems
  • 10.3 Phase Margin
  • 10.4 Basic Frequency Compensation
  • 10.5 Compensation of Two-Stage Op Amps
  • 10.6 Slewing in Two-Stage Op Amps
  • 10.7 Other Compensation Techniques
  • 10.8 Nyquist’s Stability Criterion
    • 10.8.1 Motivation
    • 10.8.2 Basic Concepts
    • 10.8.3 Construction of Polar Plots
    • 10.8.4 Cauchy’s Principle
    • 10.8.5 Nyquist’s Method
    • 10.8.6 Systems with Poles at Origin
    • 10.8.7 Systems with Multiple 180° Crossings

11. Nanometer Design Studies

• 11. Nanometer Design Studies
  • 11.1 Transistor Design Considerations
  • 11.2 Deep-Submicron Effects
  • 11.3 Transconductance Scaling
  • 11.4 Transistor Design
    • 11.4.1 Design for Given Ip and Vps,mir
    • 11.4.2 Design for Given gm and ID
    • 11.4.3 Design for Given gm and Vps.mi
    • 11.4.4 Design for a Given gm
    • 11.4.5 Choice of Channel Length
  • 11.5 Op Amp Design Examples
    • 11.5.1 Telescopic Op Amp
    • 11.5.2 Two-Stage Op Amp
  • 11.6 High-Speed Amplifier
    • 11.6.1 General Considerations
    • 11.6.2 Op Amp Design
    • 11.6.3 Closed-Loop Small-Signal Performance
    • 11.6.4 Op Amp Scaling
    • 11.6.5 Large-Signal Behavior
  • 11.7 Summary

12. Bandgap References

• 12. Bandgap References
  • 12.1 General Considerations
  • 12.2 Supply-Independent Biasing
  • 12.3 Temperature-Independent References
    • 12.3.1 Negative-TC Voltage
    • 12.3.2 Positive-TC Voltage
    • 12.3.3 Bandgap Reference
  • 12.4 PTAT Current Generation
  • 12.5 Constant-Gm Biasing
  • 12.6 Speed and Noise Issues
  • 12.7 Low-Voltage Bandgap References
  • 12.8 Case Study

13. Introduction to Switched-Capacitor Circuits

• 13. Introduction to Switched-Capacitor Circuits
  • 13.1 General Considerations
  • 13.2 Sampling Switches
    • 13.2.1 MOSFETs as Switches
    • 13.2.2 Speed Considerations
    • 13.2.3 Precision Considerations
    • 13.2.4 Charge Injection Cancellation
  • 13.3 Switched-Capacitor Amplifiers
    • 13.3.1 Unity-Gain Sampler/Buffer
    • 13.3.2 Noninverting Amplifier
    • 13.3.3 Precision Multiply-by-Two Circuit
  • 13.4 Switched-Capacitor Integrator
  • 13.5 Switched-Capacitor Common-Mode Feedback

14. Nonlinearity and Mismatch

• 14. Nonlinearity and Mismatch
  • 14.1 Nonlinearity
    • 14.1.1 General Considerations
    • 14.1.2 Nonlinearity of Differential Circuits
    • 14.1.3 Effect of Negative Feedback on Nonlinearity
    • 14.1.4 Capacitor Nonlinearity
    • 14.1.5 Nonlinearity in Sampling Circuits
    • 14.1.6 Linearization Techniques
  • 14.2 Mismatch
    • 14.2.1 Effect of Mismatch
    • 14.2.2 Offset Cancellation Techniques
    • 14.2.3 Reduction of Noise by Offset Cancellation
    • 14.2.4 Alternative Definition of CMRR

15. Oscillators

• 15. Oscillators
  • 15.1 General Considerations
  • 15.2 Ring Oscillators

  • 15.3 LC Oscillators

    • 15.3 LC Oscillators (continued)

      • 15.3.1 Basic Concepts
      • 15.3.2 Cross-Coupled Oscillator
      • 15.3.3 Colpitts Oscillator

      • 15.3.4 One-Port Oscillators

        • 15.4 Voltage-Controlled Oscillators
          • 15.4.1 Tuning in Ring Oscillators
          • 15.4.2 Tuning in LC Oscillators

    • 15.5 Mathematical Model of VCOs

16. Phase-Locked Loops

• 16. Phase-Locked Loops
  • 16.1 Simple PLL
    • 16.1.1 Phase Detector
    • 16.1.2 Basic PLL Topology
    • 16.1.3 Dynamics of Simple PLL
  • 16.2 Charge-Pump PLLs
    • 16.2.1 Problem of Lock Acquisition
    • 16.2.2 Phase/Frequency Detector
    • 16.2.3 Charge Pump
    • 16.2.4 Basic Charge-Pump PLL
  • 16.3 Nonideal Effects in PLLs
    • 16.3.1 PFD/CP Nonidealities
    • 16.3.2 Jitter in PLLs
  • 16.4 Delay-Locked Loops
  • 16.5 Applications
    • 16.5.1 Frequency Multiplication and Synthesis
    • 16.5.2 Skew Reduction
    • 16.5.3 Jitter Reduction

17. Short-Channel Effects and Device Models

• 17. Short-Channel Effects and Device Models
  • 17.1 Scaling Theory
  • 17.2 Short-Channel Effects
    • 17.2.1 Threshold Voltage Variation
    • 17.2.2 Mobility Degradation with Vertical Field
    • 17.2.3 Velocity Saturation
    • 17.2.4 Hot Carrier Effects
    • 17.2.5 Output Impedance Variation with Drain-Source Voltage
  • 17.3 MOS Device Models
    • 17.3.1 Level 1 Model
    • 17.3.2 Level 2 Model
    • 17.3.3 Level 3 Model
    • 17.3.4 BSIM Series
    • 17.3.5 Other Models
    • 17.3.6 Charge and Capacitance Modeling
    • 17.3.7 Temperature Dependence
  • 17.4 Process Corners

18. CMOS Processing Technology

• 18. CMOS Processing Technology
  • 18.1 General Considerations
  • 18.2 Wafer Processing
  • 18.3 Photolithography
  • 18.4 Oxidation
  • 18.5 Ion Implantation
  • 18.6 Deposition and Etching
  • 18.7 Device Fabrication
    • 18.7.1 Active Devices
    • 18.7.2 Passive Devices
    • 18.7.3 Interconnects
  • 18.8 Latch-Up

19. Layout and Packaging

• 19. Layout and Packaging
  • 19.1 General Layout Considerations
    • 19.1.1 Design Rules
    • 19.1.2 Antenna Effect
  • 19.2 Analog Layout Techniques
    • 19.2.1 Multifinger Transistors
    • 19.2.2 Symmetry
    • 19.2.3 Shallow Trench Isolation Issues
    • 19.2.4 Well Proximity Effects
    • 19.2.5 Reference Distribution
    • 19.2.6 Passive Devices
    • 19.2.7 Interconnects
    • 19.2.8 Pads and ESD Protection
  • 19.3 Substrate Coupling
  • 19.4 Packaging